An inter-integrated circuit (I2C) bus is a commonly used two-wire serial bus that has a simple, low-bandwidth, short-distance protocol. Using the addressing scheme associated with I2C, multiple devices may be linked together relatively easily without the need for chip select or arbitration logic.
I2C bus systems include at least one master device and one or more slave devices. With each transaction, the master device transmits the device address of the intended slave. Each slave device is then responsible for monitoring the bus and responding only when its address is transmitted with the transaction.
Each slave device generally has a predefined address, with the exception of the lower bits that may be configurable at the board level. Thus, the I2C addressing scheme limits the number of identical slave devices that may be supported on an I2C bus without contention based on the number of user-configurable address bits. This number is typically two bits, which limits the number of identical slave devices to four.
One solution to allow additional devices of the same type to have unique device addresses is to include additional address pins on the slave devices. However, this solution may be costly, especially when the number of identical devices is large. A second solution involves the use of a dedicated I2C multiplexer that breaks the system into sub-branches. However, this solution increases the system busing (adds a clock and a data line) for each multiplexer used, thereby raising the system cost and complexity.
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